Array substrate, manufacturing method thereof, display panel and display device

ABSTRACT

An array substrate, a manufacturing method thereof, a display panel and a display device are disclosed. The array substrate includes a base substrate, a light shielding layer, an active layer of a thin film transistor, and an insulating layer. The light shielding layer includes light transmission holes on the base substrate. The active layer of the thin film transistor is located on the side of the light shielding layer away from the base substrate. An insulating layer is located on the base substrate. The insulating layer includes a first through hole in communication with the light transmission hole.

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent application claims the priority of Chinese patentapplication No. 201810473898.2, entitled “array substrate andmanufacturing method thereof, display panel and display device”, filedon May 17, 2018, and the disclosure of the above-mentioned Chinesepatent application is incorporated herein by reference in its entiretyas part of the embodiment of this disclosure.

TECHNICAL FIELD

The embodiments of the disclosure relate to an array substrate, amanufacturing method thereof, a display panel and a display device.

BACKGROUND

With the rapid development of mobile payment and mobile informationexchange, the demand for convenient and effective security technologiessuitable for display devices is also increasing day by day. Fingerprintidentification technology, palmprint identification technology and irisidentification technology and other human biometric identificationtechnologies are gradually adopted by mobile electronic devices.

If a separate imaging module is introduced to enable the display deviceto have human body biometric identification functions such asfingerprint identification or palm print identification, the volume,weight, cost and power consumption of the display device will beincreased, which is contrary to the requirements and expectations ofcurrent consumers for electronic products, especially consumerelectronic products.

The display device based on the in-screen fingerprint identificationtechnology does not need to be provided with a separate fingerprintidentification module, thus having the advantages of small size of thelower frame of the screen, easy realization of full screen, oil stainresistance, water stain resistance, dust resistance and the like. Due tothe above advantages, the display device based on the in-screenfingerprint identification technology has attracted wide attention.

SUMMARY

At least an embodiment of the present disclosure provides an arraysubstrate including: a base substrate; a light shielding layer, which ison the base substrate and comprises a light transmission hole; an activelayer of a thin film transistor, located at one side of the lightshielding layer away from the base substrate; and an insulating layerlocated on the base substrate, the insulating layer including a firstthrough hole, and the first through hole being in communication with thelight transmission hole.

In some embodiments of the present disclosure, the orthographicprojection of the first through hole on the base substrate and theorthographic projection of the active layer on the base substrate do notoverlap.

In some embodiments of the present disclosure, the orthogonal projectionof the light transmission hole on the base substrate is completelywithin the orthogonal projection of the first through hole on the basesubstrate.

In some embodiments of the present disclosure, the array substratefurther includes a filling structure filled in the first through holeand the light transmission hole.

In some embodiments of the present disclosure, the first through holeand the light transmitting hole are completely filled by the fillingstructure.

In some embodiments of the present disclosure, the array substratefurther includes a filling layer located on a side of the insulatinglayer away from the base substrate, and the filling structure isintegrally formed with the filling layer.

In some embodiments of the present disclosure, the fill layer includesany one of a group consisting of a passivation layer, a gate insulatinglayer, an interlayer insulating layer, and a planarization layer.

In some embodiments of the present disclosure, the insulating layerincludes at least one of a group consisting of a buffer layer, apassivation layer, a gate insulating layer, and an interlayer insulatinglayer.

In some embodiments of the present disclosure, the array substratefurther includes a source electrode and a drain electrode, and thesource electrode and the drain electrode are respectively connected tothe active layer through second through holes penetrating at least oneof the passivation layer, the gate insulating layer, and the interlayerinsulating layer.

In some embodiments of the present disclosure, the array substratefurther includes a connection electrode connected to the light shieldinglayer through a third through hole penetrating at least one of thebuffer layer, the passivation layer, the gate insulating layer, and theinterlayer insulating layer.

In some embodiments of the present disclosure, the light transmissionholes are located at least partially between pixels of the arraysubstrate.

In some embodiments of the present disclosure, the array substratefurther includes an imaging device formed on a side of the basesubstrate away from the light shielding layer, the imaging device andthe light transmission hole at least partially overlapping in adirection perpendicular to the base substrate.

At least an embodiment of the present disclosure also provides a displaypanel including any of the above array substrates.

At least an embodiment of the present disclosure also provides a displaydevice including any of the above array substrates or any of the abovedisplay panels.

At least an embodiment of the present disclosure also provides amanufacturing method of the array substrate, including: providing a basesubstrate; forming a light shielding film layer on the base substrate;forming an active layer of a thin film transistor on the light shieldingthin film layer; and after the active layer is formed, pattering thelight shielding film layer to form a light shielding layer. The lightshielding layer comprises a light transmission hole.

In some embodiments of the present disclosure, the method furtherincludes forming an insulating layer, patterning the insulating layer toform a first through hole therein, and patterning the light shieldingthin film layer through the first through hole to form the lighttransmission hole, and the orthogonal projection of the first throughhole on the base substrate and the orthogonal projection of the activelayer on the base substrate do not overlap.

In some embodiments of the present disclosure, the method furtherincludes forming a filling structure filled in the first through holeand the light transmission hole.

In some embodiments of the present disclosure, the filling structurecompletely fills the first through hole and the light transmitting hole.

In some embodiments of the present disclosure, the method furtherincludes forming a filling layer on the insulating layer, wherein thefilling structure is part of the filling layer.

In some embodiments of the present disclosure, the fill layer includesany one of a group consisting of a passivation layer, a gate insulatinglayer, an interlayer insulating layer, and a planarization layer.

In some embodiments of the present disclosure, forming the insulatinglayer includes forming at least one of a group consisting of a bufferfilm layer, a passivation film layer, a gate insulating film layer, andan interlayer insulating film layer.

In some embodiments of the present disclosure, the method furtherincludes forming a connection electrode and forming a third through holepenetrating at least one of the buffer film layer, the passivation filmlayer, the gate insulating film layer, and the interlayer insulatingfilm layer; and the connection electrode is connected to the lightshielding layer through the third through hole.

In some embodiments of the present disclosure, the method furtherincludes providing an imaging device on a side of the base substrateaway from the light shielding layer, the imaging device at leastpartially overlapping the light transmission hole in a directionperpendicular to the base substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly explain the technical scheme of the embodimentsof the present disclosure, the following will briefly introduce thedrawings of the embodiments. Obviously, the drawings in the followingdescription only refer to some embodiments of the present disclosure,and not to the limitations of the present disclosure.

FIG. 1A is a display device having a fingerprint identificationfunction;

FIG. 1B is an exemplary structural diagram of the drive backplateillustrated in FIG. 1A;

FIG. 2A to FIG. 2E are schematic diagrams of a manufacturing method of adriving backplate;

FIG. 3A is an exemplary flowchart of a manufacturing method of an arraysubstrate provided by at least an embodiment of the present disclosure;

FIG. 3B is an exemplary structural diagram of an array substrateprovided by at least an embodiment of the present disclosure;

FIG. 3C is an exemplary plan view of an array substrate provided by atleast an embodiment of the present disclosure;

FIG. 3D is a schematic view of the filling structure and planarizationlayer illustrated in FIG. 3B;

FIG. 4A to FIG. 4O are schematic diagrams of a manufacturing method ofan array substrate provided by at least an embodiment of the presentdisclosure;

FIG. 5A is another exemplary structural diagram of an array substratemanufactured by the manufacturing method of the array substrateaccording to at least an embodiment of the present disclosure;

FIG. 5B is still another exemplary structural diagram of an arraysubstrate manufactured by the manufacturing method of the arraysubstrate according to at least an embodiment of the present disclosure;

FIG. 5C is yet another exemplary structural diagram of an arraysubstrate manufactured by the manufacturing method of the arraysubstrate according to at least an embodiment of the present disclosure;

FIG. 5D is yet another exemplary structural diagram of the arraysubstrate manufactured by the manufacturing method of the arraysubstrate according to at least an embodiment of the present disclosure;and

FIG. 6 is a schematic block diagram of a display panel and a displaydevice provided by at least an embodiment of the present disclosure.

DETAILED DESCRIPTION

In order to make objects, technical solutions and advantages of theembodiments of the present disclosure apparent, the technical solutionsof the embodiments will be described in a clearly and fullyunderstandable way in connection with the drawings related to theembodiments of the present disclosure. Apparently, the describedembodiments are just a part but not all of the embodiments of thepresent disclosure. Based on the described embodiments herein, thoseskilled in the art can obtain other embodiment(s), without any inventivework, which should be within the scope of the present disclosure.

Unless otherwise defined, all the technical and scientific terms usedherein have the same meanings as commonly understood by one of ordinaryskill in the art to which the present invention belongs. The terms“first,” “second,” etc., which are used in the description and theclaims of the present application for invention, are not intended toindicate any sequence, amount or importance, but distinguish variouscomponents. Also, the terms such as “a,” “an,” etc., are not intended tolimit the amount, but indicate the existence of at least one. The terms“comprise,” “comprising,” “include,” “including,” etc., are intended tospecify that the elements or the objects stated before these termsencompass the elements or the objects and equivalents thereof listedafter these terms, but do not preclude the other elements or objects.The phrases “connect”, “connected”, etc., are not intended to define aphysical connection or mechanical connection, but may include anelectrical connection, directly or indirectly. “On,” “under,” “right,”“left” and the like are only used to indicate relative positionrelationship, and when the position of the object which is described ischanged, the relative position relationship may be changed accordingly.

FIG. 1A is a display device with on-screen fingerprint identificationfunction. As illustrated in FIG. 1A, the display device includes adriving backplate 581, a light emitting layer 553, a laminated filmlayer 582, and a cover plate 583. For example, the light emitting layer553 may include a plurality of light emitting units (not illustrated inthe figure). For example, the driving backplate 581 may include a lightshielding layer 513, thin film transistors 512 (see FIG. 1B), and animaging device 515. The light shielding layer 513 may include aplurality of light transmitting regions (i.e., holes) and lightshielding regions 584 for spacing the plurality of light transmittingregions. The thin film transistors 512 may be used in a display drivingcircuit to drive a plurality of light emitting units to emit light. Theimaging device 515 may include a plurality of imaging pixels. Forexample, the cover plate 583 can be used to protect the related filmlayers of the display device from being scratched. The laminated filmlayer 582 may include a packaging layer or the like to alleviateoxidation problems caused by water vapor or oxygen in air. According toactual application requirements, the laminated film 582 may also includeother film layers (e.g., electrode layers), which are not described indetail herein.

For example, light rays incident on the skin of a finger (e.g., lightrays emitted by the light emitting units) will be diffusely reflected,and part of the diffusely reflected light rays returns to the displaydevice and be incident on the imaging device 515 (see FIG. 2D) via thelight transmitting region of the light shielding layer 513 (i.e., theholes 514 of the light shielding layer), whereby the imaging device 515can image the fingerprint of the finger, and further the display deviceillustrated in FIG. 1A can realize the on-screen fingerprintidentification function.

FIG. 1B is an exemplary structural diagram of the drive backplate 581illustrated in FIG. 1A. As illustrated in FIG. 1B, the driving backplate581 includes a base substrate 511, a light shielding layer 513, a bufferlayer 521, an active layer 516 of a thin film transistor 512, a gateinsulating layer 522 of the thin film transistor 512, a gate electrode523 of the thin film transistor 512, a passivation layer 524 of the thinfilm transistor 512, an interlayer insulating layer 525, a sourceelectrode 529 and a drain electrode 5 of the thin film transistor 512, aplanarization layer 527, a first electrode 552, and a pixel defininglayer 555. For example, the light shielding layer 513 includes a lightshielding region 584 that may include a plurality of light transmittingregions (i.e., a plurality of holes 514) and is used to space theplurality of light transmitting regions. For example, the lightshielding layer 513 may be made of metal, but according to actualapplication requirements, the light shielding layer 513 may also be madeof other materials having a light shielding function.

The inventors have noted that for the current manufacturing process ofthe driving backplate 581, in order to ensure the performance of thethin film transistor 512, a large spacing needs to be reserved betweenthe orthogonal projection of the active layer 516 of the thin filmtransistor 512 on the light shielding layer 513 and the lighttransmission regions (i.e., the holes 514 of the light shielding layer)of the adjacent light shielding layer 513. Based on a given resolution,this makes the diameter of the light transmission region (i.e., the holeof the light shielding layer) of the light shielding layer 513 smaller.Thus, the intensity of diffuse reflection light, which is from a fingerand incident on the imaging device 515, is made small, thereby makingthe imaging quality of the imaging device 515 poor (e.g., thesignal-to-noise ratio of the image output by the imaging device 515 issmall).

The inventors also noted that in order to avoid parasitic capacitancecaused by floating of the light shielding layer 513 and warping effectof the thin film transistor 512, the light shielding layer 513 can beelectrically connected through the connection electrode 571 electricallyconnected to the light shielding layer 513 to release the electriccharge accumulated on the light shielding layer 513. However, theinventors have noted that in order to form the connection electrode 571,at least one additional patterning process is required. Considering thatat least one additional patterning process is required in order to formthe hole 514 of the light shielding layer, at least two additionalpatterning processes are required in order to manufacture the drivingbackplate 581 and the display device with the on-screen fingerprintidentification function, which will greatly reduce the manufacturingefficiency of the driving backplate 581 and the display device andincrease the required manufacturing cost.

Next, a method for solving at least one of the above problems will beexemplarily described with reference to FIG. 2A to FIG. 2D. For example,FIG. 2A to FIG. 2D show a manufacturing method of a driving backplate581. For example, as illustrated in FIG. 2A to FIG. 2D, themanufacturing method of the driving backplate 581 may include thefollowing steps.

Step S511: a base substrate 511 is provided (see FIG. 2A). In order tofacilitate explanation of the positions of various structures formedsubsequently, the imaging device 515 is illustrated in FIG. 2A, but theimaging device 515 may be arranged subsequently.

Step S512: a light shielding layer 513 of a metal material (e.g., metalMo) is formed on the base substrate 511, and the light shielding layer513 is patterned to form a hole 514 (see FIG. 2A).

Step S513: a buffer layer 521 made of an insulating material is formedon the light shielding layer 513, and an active layer 516 of the thinfilm transistor 512 is formed on the buffer layer 521 (see FIG. 2B).

Step S514: the buffer layer 521 is patterned to form a third via hole533 (see FIG. 2B) to expose the light shielding layer 513.

Step S515: a gate insulating layer 522 of the thin film transistor 512,a gate electrode 523 of the thin film transistor 512, a passivationlayer 524 of the thin film transistor 512, and an interlayer insulatinglayer 525 are sequentially formed on the active layer 516 of the thinfilm transistor 512 (see FIG. 2C).

Step S516: the gate insulating layer 522 of the thin film transistor512, the passivation layer 524 of the thin film transistor 512, and theinterlayer insulating layer 525 are patterned to form second via holes531 and a fourth via hole 534 (see FIG. 2C).

Step S517: a source electrode 529 and a drain electrode 5 contacting theactive layer 516 through the second via holes 531 are formed in thedisplay region 561, and a connection electrode 571 contacting the lightshielding layer 513 through the third via hole 533 and the fourth viahole 534 is formed in the peripheral region 562 (see FIG. 2D).

Step S518: a planarization layer 527, a first electrode 552, and a pixeldefining layer 555 are formed on the source electrode 529, the drainelectrode 5 and the connection electrode 571, and the first electrode552 is connected to the source or drain through a via hole in theplanarization layer 527 (see FIG. 2D).

For example, in step S513, forming the active layer 516 of the thin filmtransistor 512 on the buffer layer 521 includes forming an amorphoussilicon layer on the buffer layer 521 and performing an annealingprocess on the amorphous silicon layer to convert the amorphous siliconlayer into a polysilicon layer. For example, performing an annealingprocess on the amorphous silicon layer includes irradiating theamorphous silicon layer with laser light (e.g., laser light output froman excimer laser), the amorphous silicon layer absorbs the laser lightand generates heat, and gradually changes from a surface melting stateto a completely melting state, and the amorphous silicon layer changesinto a polysilicon layer in the cooling process.

The inventors have noted that because there are a plurality of holes inthe light shielding layer 513, during laser irradiation of the amorphoussilicon layer, there is a temperature difference (e.g., a temperaturegradient) between the region of the light shielding layer 513 close tothe hole 514 of the light shielding layer and the region away from thehole 514 of the light shielding layer, and thus the grain morphology ofthe region of the polysilicon layer close to the hole 514 of the lightshielding layer (e.g., the region where the distance between theorthogonal projection on the light shielding layer 513 and the hole 514of the light shielding layer is less than, for example, 1 micron) isadversely affected, thereby deteriorating the performance of the thinfilm transistor 512. FIG. 2E shows a Scanning Electron Microscope (SEM)photograph of a polycrystalline silicon layer that is obtained bycrystallizing an amorphous silicon layer and covers a hole in a lightshielding layer, and it can be seen that polycrystalline silicon grainscorresponding to the inside of the hole (circular part in thephotograph) and the edge part of the hole are affected differently fromother parts.

Therefore, in order to ensure the performance of the thin filmtransistor 512, the orthogonal projection of the active layer 516 of thethin film transistor 512 on the light shielding layer 513 is between thelight transmitting regions of the adjacent light shielding layer 513.The pitch PD that needs to be reserved needs to include not only thefirst predetermined pitch PD1 (e.g., 0.6 microns) corresponding to theprocess accuracy error, but also the second predetermined pitch PD2(e.g., 1 micron or 2 microns) corresponding to the annealing temperaturedifference (e.g., temperature gradient). Because the additional secondpredetermined pitch PD2 makes the diameter of the light transmittingregion of the light shielding layer 513 smaller (e.g., 6.5 microns or5.5 microns), the intensity of the diffuse reflection light that is froma finger and incident on the imaging device 515 is reduced, therebyreducing the signal-to-noise ratio of the image output by the imagingdevice 515.

In addition, because the patterning of the light shielding layer 513 andthe patterning of the buffer layer 521 are two separate processes, andat least one additional patterning process is required to form the hole514 of the light shielding layer, at least two additional patterningprocesses are required to manufacture the driving backplate 581 and thedisplay device with the on-screen fingerprint identification function.However, in order to manufacture the driving backplate 581 and thedisplay device with the on-screen fingerprint identification functionand the suppressed warping effect of the thin film transistor, at leastthree additional patterning processes are required, which will greatlyreduce the manufacturing efficiency of the driving backplate 581 and thedisplay device and increase the required manufacturing costs.

For example, in FIG. 1B, FIG. 2B, FIG. 2C and FIG. 2D, the holes 514 inthe light shielding layer may also be filled with the material of thebuffer layer 521.

The embodiments of the disclosure provide an array substrate, amanufacturing method thereof, a display panel and a display device. Thearray substrate, the manufacturing method thereof, the display panel andthe display device can improve the imaging quality.

At least an embodiment of the present disclosure provides that the arraysubstrate includes a base substrate, a light shielding layer, an activelayer of a thin film transistor, and an insulating layer. The lightshielding layer is on the base substrate and comprises lighttransmission holes. The active layer of the thin film transistor islocated on the side of the light shielding layer away from the basesubstrate. An insulating layer is located on the base substrate. Theinsulating layer comprises a first through hole, and the first throughhole is communicated with the light transmission hole.

At least an embodiment of the present disclosure provides an arraysubstrate including a base substrate, a light shielding layer, and athin film transistor. The light shielding layer is arranged between thebase substrate and the thin film transistor and comprises a lighttransmission hole; the thin film transistor comprises an active layerand a passivation layer which are sequentially arranged on one side ofthe light shielding layer which is far away from the base substrate, thepassivation layer is positioned on one side of the active layer which isfar away from the base substrate; the passivation layer comprises afirst via hole, and the first via hole is communicated with the lighttransmission hole. In the embodiment of the present disclosure, thefirst via hole can be used to form the light transmission hole. Thefirst via hole is located in an area outside the region where the thinfilm transistor is located.

For example, the orthographic projection of the light transmission holeof the light-shielding layer on the base substrate is completely withinthe orthographic projection of the first via hole on the base substrate,but the disclosure is not limited thereto. For example, the lighttransmission hole may be formed by patterning the light-shielding layerthrough the first via hole. Due to the etching process adopted, theorthogonal projection of the light transmission hole of the lightshielding layer on the base substrate may be slightly different from theorthogonal projection of the first via hole on the base substrate.

The array substrate according to the embodiments of the presentdisclosure will be described below by several examples withoutlimitation. As described below, different features in these specificexamples can be combined with each other without conflict, so as toobtain new examples, which are also within the scope of protection ofthe present disclosure.

As illustrated in FIG. 3B, the array substrate 100 includes a basesubstrate 111, a light shielding layer 113, and a thin film transistor112. The light shielding layer 113 is between the base substrate 111 andthe thin film transistor 112 and includes a light transmission hole 114.The thin film transistor 112 includes an active layer 116 and apassivation layer 124 sequentially disposed on a side of the lightshielding layer 113 away from the base substrate 111. For example, theactive layer 116 is a semiconductor layer. For example, the active layer116 may include a polysilicon layer, and the polysilicon layer may beformed of an amorphous silicon layer by an annealing process. Forexample, the fabrication methods of the base substrate 111, the lightshielding layer 113 and the thin film transistor 112 can be seen in thefabrication method of the array substrate provided in the embodiment ofthe present disclosure, and will not be described here again.

As illustrated in FIG. 3B, the passivation layer 124 includes a firstvia hole 132; the orthographic projection of the light transmission hole114 of the light-shielding layer on the base substrate 111 is completelywithin the orthographic projection of the first via hole 132 on the basesubstrate 111, but the disclosure is not limited thereto. For example,by providing the first via hole 132 in the passivation layer 124, thelight shielding layer 113 can be patterned to form the lighttransmitting hole 114 after forming the active layer of the thin filmtransistor (e.g., forming the passivation layer 124), whereby in theannealing process for forming the active layer, the light shieldinglayer will not cause a temperature difference, thus not affecting thecrystal morphology of different parts of the active layer. Therefore,the light shielding layer does not adversely affect the formation of theactive layer of the thin film transistor, thereby reducing the adverseeffect of the light transmission hole of the light shielding layer onthe active layer without reducing the diameter of the light transmissionhole of the light shielding layer, further improving the intensity ofthe diffuse reflection light that is from a finger and incident on theimaging device and correspondingly improving the signal-to-noise ratioof image output by the imaging device. The following description will bemade in connection with different embodiments.

It should be noted that the embodiments of the present disclosure aredescribed by taking the light transmission hole 114 of thelight-shielding layer in a circular shape as an example, but theembodiment of the present disclosure is not limited to this, and thelight transmission hole 114 of the light-shielding layer may also beoval, square, etc. according to actual application requirements.

As illustrated in FIG. 3B, the orthogonal projection of the first viahole 132 on the base substrate 111 and the orthogonal projection of theactive layer 116 on the base substrate 111 do not overlap. For example,the first via hole 132 is located between adjacent thin filmtransistors. Furthermore, for example, the first via hole 132 is locatedbetween the active layers 116 of adjacent thin film transistors.

For example, the orthogonal projection of the light transmission hole114 of the light-shielding layer on the base substrate 111 maycompletely overlap with the orthogonal projection of the first via hole132 on the base substrate 111. In this case, the orthogonal projectionof the light transmission hole 114 of the light-shielding layer on thebase substrate 111 has the same shape and size as the orthogonalprojection of the first via hole 132 on the base substrate 111, therebysimplifying the manufacturing process.

As illustrated in FIG. 3B, the thin film transistor 112 further includesa gate insulating layer 122 and a gate electrode 123 disposed betweenthe active layer 116 and the passivation layer 124, and a sourceelectrode 129 and a drain electrode 126 disposed on a side of thepassivation layer 124 away from the active layer 116. The first via hole132 is formed passing through the gate insulating layer 122; the sourceelectrode 129 and the drain electrode 126 are in contact with the activelayer 116 through the second via holes 131 formed in the gate insulatinglayer 122 and the passivation layer 124.

As illustrated in FIG. 3B, the array substrate 100 further includes aninterlayer insulating layer 125, a first capacitor electrode 141, and asecond capacitor electrode 142. The first capacitor electrode 141 andthe second capacitor electrode 142 may at least partially overlap (e.g.,completely overlap) in a direction perpendicular to the base substrate111 to form a capacitor, which may be used, for example, to realizesignal storage, threshold compensation function, and the like of a pixelcircuit.

As illustrated in FIG. 3B, the interlayer insulating layer 125 isdisposed between the passivation layer 124 and the layer where thesource electrode 129 and the drain electrode 126 are located. The firstcapacitor electrode 141 is disposed between the gate insulating layer122 and the passivation layer 124. In this case, the first capacitorelectrode 141 may be formed in the first patterning process of formingthe gate electrode 123, thereby reducing process complexity. The secondcapacitor electrode 142 is disposed between the passivation layer 124and the interlayer insulating layer 125. In this case, the secondcapacitor electrode 142 is formed in the second patterning process offorming the light transmission hole 114 of the light-shielding layer,thereby further reducing process complexity.

As illustrated in FIG. 3B and FIG. 3D, the array substrate 100 furtherincludes a filling structure 199 filled in the first via hole 132 andthe light transmission hole 114, i.e., the filling structure 199 passesthrough the passivation layer 124 and the light-shielding layer 113. Inthis case, the first via hole 132 passing through the above-mentionedlayers is filled with a single material, thereby avoiding the phenomenonthat the intensity of light passing through the light transmission hole114 of the light-shielding layer decreases due to interfacial reflectionbetween various film layers (e.g., interfacial reflection between thegate insulating layer 122 and the passivation layer 124) over the lighttransmission hole 114. Therefore, by providing the filling structure 199in the first via hole 132, the intensity of the diffuse reflection lightthat is from a finger and incident on the imaging device 115 is furtherincreased, and the signal-to-noise ratio of the image output by theimaging device 115 is improved. For example, as illustrated in FIG. 3B,the first via hole 132 and the light transmission hole 114 arecompletely filled by the filling structure 199.

As illustrated in FIG. 3B, the array substrate 100 further includes aplanarization layer 127 disposed on a side of the interlayer insulatinglayer 125 away from the active layer 116. In this case, the first viahole 132 may be filled with a material for forming the planarizationlayer 127. That is, the planarization layer 127 and the fillingstructure 199 are made of the same material, and the surfaces of thefilling structure 199 opposite to each other in the directionperpendicular to the base substrate 111 are in contact with theplanarization layer 127 and the base substrate 111, respectively.Because the planarization layer 127 and the filling structure 199 areintegrally formed, there may be no interface between the planarizationlayer 127 and the filling structure 199. For example, the planarizationlayer 127 here may be used as the filling layer FL to fill the first viahole 132 and the light transmission hole 114, but in the embodiments ofthe present disclosure, the filling layer FL may not use theplanarization layer 127, but may use a layer of another insulatingmaterial. For example, the filling layer FL may also adopt any one ofthe passivation layer 124, the gate insulating layer 122, and theinterlayer insulating layer 125, which will be described in thefollowing embodiments.

By providing the filling structure 199 in contact with the planarizationlayer 127 and the base substrate 111, it is possible to prevent thelight intensity through the light transmission hole 114 of thelight-shielding layer from decreasing due to the interfacial reflectionbetween the plurality of film layers. For example, the interfacereflection between the plurality of film layers includes the interfacereflection between the buffer layer 121 and the gate insulating layer122, the interface reflection between the passivation layer 124 and thegate insulating layer 122, the interface reflection between theinterlayer insulating layer 125 and the passivation layer 124, and theinterface reflection between the planarization layer 127 and theinterlayer insulating layer 125. Therefore, it is possible to furtherincrease the intensity of the diffuse reflection light that is from afinger and incident on the imaging device 115 and the signal-to-noiseratio of the image output by the imaging device 115.

It should be noted that in other embodiments not illustrated, the lighttransmission hole 114 in the light-shielding layer may be filled with amaterial for forming the gate insulating layer 124, the passivationlayer 124 or the interlayer insulating layer 127 according to therelationship between the step of forming the light transmission hole 114in the light-shielding layer and other steps.

As illustrated in FIG. 3B, the array substrate 100 includes a displayregion 161 and a peripheral region 162; the display area 161 may includedisplay pixels arranged in an array, and each display pixel may includeat least one light emitting element; the peripheral region 162 may bedisposed around the display region 161.

As illustrated in FIG. 3B, the array substrate 100 further includes athird via hole 133 located in the gate insulating layer 122 and thepassivation layer 124, a fourth via hole 134 located in the interlayerinsulating layer 125, and a connection electrode 171 formed after theinterlayer insulating layer 125 is formed and before the planarizationlayer 127.

As illustrated in FIG. 3B, the orthogonal projection of the third viahole 133 on the base substrate 111 and the orthogonal projection of thefourth via hole 134 on the base substrate 111 at least partiallyoverlap, in which case, the connection electrode 171 may contact thelight shielding layer 113 through the third via hole 133 and the fourthvia hole 134 (through the electrode filling structure 198 provided inthe third via hole 133 and the fourth via hole 134), therefore, thelight shielding layer 113 can be electrically connected via theconnection electrode 171 and the electric charge accumulated on thelight shielding layer 113 can be released, thereby avoiding parasiticcapacitance caused by floating of the light shielding layer 113 andwarping effect of the thin film transistor 112, and further improvingthe display quality.

As illustrated in FIG. 3B, the third via hole 133 and the fourth viahole 134 are located in the peripheral region 162 of the array substrate100, whereby the influence on the normal display of the display region161 can be avoided. The connection electrode 171 may contact the lightshielding layer 113 via the fourth via hole 134 and the third via hole133, but embodiments of the present disclosure are not limited thereto.

As illustrated in FIG. 3B, the orthographic projection of the third viahole 133 on the base substrate 111 is completely within the orthographicprojection of the fourth via hole 134 on the base substrate 111, therebyimproving the uniformity of the filling structure 198 and further betterreleasing the charge accumulated on the light shielding layer 113, butthe embodiment of the present disclosure is not limited thereto.

In the embodiment of the present disclosure, the insulating layer mayinclude at least one layer or may be a laminated structure. For example,the insulating layer ISL in FIG. 3B includes a buffer layer 121, apassivation layer 124, a gate insulating layer 122, and an interlayerinsulating layer 125, and the insulating layer ISL may also include atleast one of the passivation layer 124, the gate insulating layer 122,and the interlayer insulating layer 125.

As illustrated in FIG. 3B, the first through hole H1 penetrates throughthe insulating layer ISL. For example, as illustrated in FIG. 3B, thefirst through hole H1 penetrates through the buffer layer 121, thepassivation layer 124, the gate insulating layer 122, and the interlayerinsulating layer 125. In other embodiments, the first through hole H1can be adjusted as needed according to the insulating layer ISL.

For example, the source electrode 129 and the drain electrode 126 maycontact the active layer 116 through second through holes H2 penetratingat least one of the passivation layer 124, the gate insulating layer122, and the interlayer insulating layer 125. As illustrated in FIG. 3B,the source electrode 129 and the drain electrode 126 are in contact withthe active layer 116 through the second through holes H2 penetrating thepassivation layer 124, the gate insulating layer 122, and the interlayerinsulating layer 125.

It should be noted that the specific structure of the array substrate100 is not limited to the structure illustrated in FIG. 3B. According toactual application requirements, the array substrate 100 provided by theembodiment of the present disclosure can also be implemented as thestructure illustrated in FIG. 5A to FIG. 5D, the specific structure andmanufacturing method can be referred to the manufacturing method of thearray substrate provided by the embodiment of the present disclosure,and will not be described here again.

At least an embodiment of the present disclosure further provides adisplay panel 10 and a display device 20, and FIG. 6 shows an exemplaryblock diagram of the display panel 10 and the display device 20 providedby at least an embodiment of the present disclosure. For example, asillustrated in FIG. 6, the display panel 10 includes the array substrate100 provided by any embodiment of the present disclosure, and thedisplay device 20 includes the array substrate 100 provided by anyembodiment of the present disclosure or the display panel 10 provided byany embodiment of the present disclosure. The display panel 10 and thedisplay device 20 can have improved imaging quality.

For example, the display device 20 can be any product or component witha display function such as a mobile phone, a tablet computer, atelevision, a display, a notebook computer, a digital photo frame, anavigator, etc. It should be noted that suitable conventional componentscan be used for other essential components of the display panel 10 andthe display device 20 (e.g., thin film transistor control device, imagedata encoding/decoding device, row scan driver, column scan driver,clock circuit, etc.), which should be understood by those of ordinaryskill in the art, are not described in detail herein, and should not betaken as a limitation to the present invention.

At least an embodiment of the present disclosure provides amanufacturing method of an array substrate, comprising: providing a basesubstrate; forming a light shielding layer on the base substrate; andforming a thin film transistor on the light shielding layer. Forexample, forming the thin film transistor includes forming an activelayer of the thin film transistor. The light shielding layer ispatterned to form a light transmission hole after forming an activelayer of the thin film transistor.

The manufacturing method of the array substrate according to theembodiments of the present disclosure will be described below throughseveral examples without limitation. As described below, differentfeatures in these specific examples can be combined with each otherunder the condition that they do not conflict with each other, so as toobtain new examples, which are also within the scope of protection ofthe present disclosure.

A manufacturing method of an array substrate comprises the followingsteps: providing a base substrate; forming a light shielding film layeron the base substrate; forming an active layer of a thin film transistoron the light shielding thin film layer; and after forming the activelayer, patterning the light shielding film layer to form a lightshielding layer, wherein the light shielding layer includes lighttransmission holes.

For example, as illustrated in FIG. 3A, the manufacturing method of thearray substrate provided by at least an embodiment of the presentdisclosure includes the following steps.

Step S10: a base substrate is provided.

Step S20: a light shielding film layer is formed on the base substrate.

Step S30: an active layer of a thin film transistor is formed on thelight shielding thin film layer.

Step S40: after forming the active layer, the light shielding film layeris patterned to form a light shielding layer, and the light shieldinglayer includes light transmission holes.

For example, a patterning process may be used to pattern thelight-shielding thin film layer to form light transmission holes, butembodiments of the present disclosure are not limited thereto. Forexample, the light transmission holes of the light-shielding layer maybe all disposed in the display area of the array substrate, but theembodiments of the present disclosure are not limited thereto. Forexample, according to actual application requirements, part of the lighttransmission holes of the light-shielding layer can also be arranged inthe peripheral area of the array substrate.

For example, by patterning the light-shielding thin film layer to formlight transmission holes after forming the active layer of the thin filmtransistor, the light-shielding thin film layer will not causetemperature difference in the annealing process for forming the activelayer, thus not affecting the crystal morphology of different parts ofthe active layer. Therefore, the light-shielding thin film layer doesnot adversely affect the formation of the active layer of the thin filmtransistor, thereby reducing the adverse effect of the lighttransmission hole of the light-shielding layer on the active layerwithout reducing the diameter of the light transmission hole of thelight-shielding layer, further improving the intensity of the diffusereflection light that is from a finger and incident on the imagingdevice and correspondingly improving the signal-to-noise ratio of imageoutput by the imaging device. The following description will be madewith reference to different embodiments.

FIG. 3B is an exemplary structural diagram of an array substrateaccording to at least an embodiment of the present disclosure, and thearray substrate can be obtained using the manufacturing method of thearray substrate illustrated in FIG. 3A. For example, the array substrate100 includes a base substrate 111, a light shielding layer 113, and athin film transistor 112, which are formed on the base substrate 111.For example, the array substrate 100 further includes a light emittingelement 151.

For example, the thin film transistor 112 may include a drivingtransistor for driving the light emitting element 151 to emit light, aswitching transistor for controlling whether a data signal is applied tothe driving transistor, or the like. For example, the thin filmtransistor 112 includes an active layer 116, a gate insulating layer122, a gate electrode 123, a passivation layer 124, and a sourceelectrode 129 and a drain electrode 126, which are sequentially disposedon the light shielding layer 113. Here, the source electrode 129 and thedrain electrode 126 are in contact with the active layer 116 through thesecond via holes 131 formed in the gate insulating layer 122 and thepassivation layer 124.

It should be noted that the manufacturing method of the array substrateaccording to at least an embodiment of the present disclosure is notonly suitable for manufacturing a top gate type thin film transistor asillustrated in FIG. 3B, but also suitable for manufacturing a bottomgate type thin film transistor, which will not be repeated here.

For example, the light shielding layer 113 may be made of a metalmaterial (e.g., metal molybdenum). In this case, as illustrated in FIG.3B, a buffer layer 121 is further provided between the light shieldinglayer 113 and the thin film transistor 112 to electrically insulate thelight shielding layer 113 from the thin film transistor 112. Forexample, the light shielding layer 113 may be made of a non-metallicmaterial (e.g., an opaque metal oxide such as chromium oxide), and thena buffer layer may not be provided in this example. An imaging device115 is also provided on the side of the base substrate 111 away from thelight shielding layer 113. The imaging device 115 and the lighttransmission hole 114 of the light shielding layer at least partiallyoverlap in the direction perpendicular to the base substrate 111 toincrease the intensity of the diffuse reflection light that is from afinger and incident on the imaging device 115 and to improve thesignal-to-noise ratio of image output by the imaging device 115. Forexample, the imaging device 115 may respond according to the intensityof light irradiated thereon to synthesize an image of a fingerprint andfurther for identifying the fingerprint, but the disclosure is notlimited thereto.

For example, as illustrated in FIG. 3C, the array substrate includes aplurality of light emitting elements 151, a plurality of lighttransmitting holes 114, and a plurality of imaging devices 115. Theplurality of light-emitting elements 151, the plurality of lighttransmission holes 114 and the plurality of imaging devices 115 arerespectively arranged in arrays, the orthographic projection of eachlight transmission hole 114 and the corresponding imaging device 115 onthe base substrate 111 at least partially overlaps, and the orthographicprojection of each light transmission hole 114 on the base substrate 111is arranged between the orthographic projections of the adjacentlight-emitting elements 151 on the base substrate 111. The arrangementof the plurality of light emitting elements 151 and the arrangement ofthe plurality of light transmitting holes 114 may not be limited to thatof FIG. 3C. For example, in the horizontal direction of FIG. 3C, oneimaging device 115 may be provided for every 8 through 10 light emittingelements 151.

For example, as illustrated in FIG. 3B, a planarization layer 127 and alight emitting element 151 that is in contact with the source electrodeor drain electrode of the thin film transistor 112 via hole a fifth viahole 135 in the planarization layer 127 are further provided on the sideof the thin film transistor 112 away from the base substrate 111. Forexample, the light emitting element 151 is an organic light emittingdiode, and includes a first electrode 152, a pixel defining layer 155, alight emitting layer 153, and a second electrode 154 which aresequentially arranged. The first electrode 152 and the second electrode154 may be an anode and a cathode, respectively, but embodiments of thepresent disclosure are not limited thereto. In another example, only thefirst electrode 152 and the pixel defining layer 155 may be provided onthe side of the planarization layer 127 away from the base substrate 111to form a driving backplate. In this case, the light emitting layer 153and the second electrode 154 may be formed in a subsequent manufacturingprocess.

As illustrated in FIG. 3B and FIG. 3C, the array substrate includes aplurality of pixels P, and the light transmission holes 114 are at leastpartially located between the pixels P. For example, a pixel P is thesmallest light emitting unit. The pixel P includes a light emittingelement 151, but is not limited thereto. For example, the pixel may alsobe a display pixel in a liquid crystal display device. For example, theorthogonal projection of the light transmission hole 114 on the basesubstrate may also be located within the orthogonal projection of thepixel P on the base substrate. The position of the light transmissionhole 114 can be selected as required as long as it is not shielded by alight-shielding element/component. For example, the orthogonalprojection of the light transmission hole 114 on the base substrate doesnot overlap with the orthogonal projection of the thin film transistoron the base substrate, so as to prevent light rays from being blocked byelements such as a gate electrode, a source electrode, a drain electrodeand the like of the thin film transistor from passing through the lighttransmission hole 114.

As illustrated in FIG. 3B, a first via hole 132 is formed in the bufferlayer 121, the gate insulating layer 122, the passivation layer 124, andthe interlayer insulating layer 125 to expose the light transmissionhole 114. For example, the material for forming the planarization layer127 fills the first via hole 132, that is, the first via hole 132passing through the above-mentioned layers is filled with a singlematerial, whereby the phenomenon that the intensity of light passingthrough the light transmission hole 114 of the light-shielding layerdecreases due to interfacial reflection between various film layers(e.g., interfacial reflection between the gate insulating layer 122 andthe passivation layer 124) over the light transmission hole 114 can beavoided. Therefore, by filling the first via hole 132 with the materialfor forming the planarization layer 127, the intensity of the diffusereflection light that is from a finger and incident on the imagingdevice 115 is further increased, and the signal-to-noise ratio of theimage output by the imaging device 115 is improved.

For example, as illustrated in FIG. 3B, the array substrate 100 furtherincludes a connection electrode 171 disposed in a peripheral region 162of the array substrate 100. The connection electrode 171 is in contactwith the light shielding layer 113 through the third via hole 133, andcan electrically connect the light shielding layer 113 through theconnection electrode 171 and release charges accumulated on the lightshielding layer 113, thereby avoiding parasitic capacitance caused byfloating of the light shielding layer 113 and warping effect of the thinfilm transistor 112, and further improving display quality.

In the embodiment of the present disclosure, the connection electrode171 is connected to the light shielding layer 113 through the thirdthrough hole H3. The third through hole H3 is a via hole penetrating theinsulating layer between the connection electrode 171 and the lightshielding layer. The third through hole H3 may be the third through hole133, but is not limited thereto. For example, when the connectionelectrode 171 is disposed on the same layer as the gate electrode 123,the third through hole H3 may penetrate only the gate insulating layer.

For example, as illustrated in FIG. 3B, the array substrate 100 furtherincludes a first capacitor electrode 141 and a second capacitorelectrode 142. the first capacitor electrode 141 and the secondcapacitor electrode 142 may at least partially overlap (e.g., completelyoverlap) in the direction perpendicular to the base substrate 111 toform a capacitor, which may be used to realize signal storage, thresholdcompensation function, etc. of a pixel circuit, for example.

For example, as illustrated in FIG. 3B, in a case where the arraysubstrate 100 further includes a first capacitor electrode 141 and asecond capacitor electrode 142, the array substrate 100 further includesan interlayer insulating layer 125 disposed between the passivationlayer 124 and the planarization layer 127, the first capacitor electrode141 may be disposed between the gate insulating layer 122 and thepassivation layer 124 of the thin film transistor 112, and the secondcapacitor electrode 142 may be disposed between the passivation layer124 and the interlayer insulating layer 125 of the thin film transistor112 to reduce process complexity, but the embodiments of the presentdisclosure is not limited thereto.

For example, as illustrated in FIG. 3B, the array substrate 100 furtherincludes a plurality of spacers 156 disposed on a side surface of thepixel defining layer 155 away from the base substrate 111, and includesa cover plate (not illustrated in FIG. 3B) disposed on a side surface ofthe plurality of spacers 156 away from the base substrate 111. Forexample, the orthogonal projection of each spacer 156 on the arraysubstrate 100 and the orthogonal projection of the first electrode 152on the array substrate 100 are arranged at an interval, so that theforce applied to the cover plate can be prevented from being transmittedto the light emitting layer 153, and further the display quality of thedisplay panel 10 including the array substrate 100 can be ensured. Inanother example, a plurality of spacers 156 may not be provided.

For example, the manufacturing method of an array substrate provided bythe embodiment of the present disclosure will be exemplarily describedbelow with reference to FIG. 4A to FIG. 4O, the finally obtained arraysubstrate corresponds to the array illustrated in FIG. 3B, however,corresponding modifications can be made as required, such as adding orreducing some layer structures, such as layer structures above lighttransmission holes in the light-shielding layer, etc. therefore, theembodiments of the present disclosure are not limited to the embodimentillustrated in the figure. For example, as illustrated in FIG. 4A toFIG. 4O, the manufacturing method of the array substrate may include thefollowing steps.

Step S201: a base substrate 111 is provided (see FIG. 4A).

For example, the base substrate 111 may be a flexible base substrate111, but embodiments of the present disclosure are not limited thereto.According to actual application requirements, the base substrate 111 mayalso be inflexible rigid base substrates (e.g., glass substrate andsemiconductor base substrate). For example, the flexible base substrate111 may be a metal foil, thin glass, or a plastic substrate (e.g., abase substrate made of polyimide), but embodiments of the presentdisclosure are not limited thereto. For example, the minimum value ofthe bending radius of the base substrate 111 may be between 10 mm and 30mm (e.g., 20 mm), but embodiments of the present disclosure are notlimited thereto. For example, if the minimum bending radius of the basesubstrate 111 is 20 mm and the base substrate 111 is wound around acylinder with a radius of 20 mm for 10,000 times, the base substrate 111can operate without failure.

For example, according to actual application requirements, an imagingdevice 115 may be provided on one side surface of the base substrate 111(i.e., one side surface of the base substrate 111 away from the lightshielding layer 113), and the imaging device 115 and the lighttransmission hole 114 of the light shielding layer may at leastpartially overlap in the direction perpendicular to the base substrate111. Although the imaging device 115 is illustrated in FIG. 4A, theimaging device 115 may be mounted to one side of the base substrate 111after the fabrication of the array substrate is completed.

For example, the specific structure and type of the imaging device 115can be set according to actual application requirements, and theembodiments of the present disclosure do not have specific limitation inthis aspect. For example, the imaging device 115 includes a plurality ofimaging pixels, each imaging pixel may include a photodiode that canconvert an optical signal irradiated thereon into an electrical signal,and a switching transistor that may be electrically connected to thephotodiode to control whether the photodiode is in a state of collectingan optical signal and the time period when the optical signal iscollected. For example, the type and setting mode of photodiodes can bedetermined according to actual application requirements, and theembodiments of the present disclosure are not specifically limited tothis. For example, the photodiode may be a PIN junction type photodiodeor a phototransistor, and thus the response speed of the photodiode maybe improved.

Step S202: a light shielding thin film layer 1130 is formed on the basesubstrate 111 (see FIG. 4B).

For example, the light shielding film layer 1130 may be made of metal,light absorbing material, black light shielding material, or othersuitable materials. For example, when the light shielding film layer1130 is metal, the light shielding film layer 1130 may be formed ofmolybdenum metal. For example, in the present disclosure, theembodiments of the present disclosure is described by taking the lightshielding film layer 1130 being a metal as an example, but theembodiments of the present disclosure are not limited thereto. Forexample, according to actual application requirements, before formingthe light shielding thin film layer 1130, a protection layer (notillustrated in the figure) may be formed on the base substrate 111,which can alleviate oxidation problems caused by water vapor or oxygenin air to provide an insulating function, for example.

Step S203: a buffer film layer 1210 is formed on the light shieldingfilm layer 1130 (see FIG. 4C).

For example, the buffer film layer 1210 may be made of a transparentinsulating material and used to electrically insulate the lightshielding film layer 1130 and the thin film transistor 112 disposed onopposite sides of the buffer film layer 1210. For example, the bufferfilm layer 1210 may be formed of an inorganic material or an organicmaterial, and the buffer film layer 1210 may be formed of, for example,organic resin, silicon oxide (SiOx), silicon oxynitride (SiNxOy), orsilicon nitride (SiNx), but embodiments of the present disclosure arenot limited thereto.

Step S204: the active layer 116 of the thin film transistor 112 isformed on the buffer thin film layer 1210 (see FIG. 4D).

For example, forming the active layer 116 of the thin film transistor112 includes first forming an amorphous silicon layer, then performingan annealing process on the amorphous silicon layer to convert theamorphous silicon layer into a polysilicon layer, and then patterningthe polysilicon layer to obtain a patterned active layer. For example,performing an annealing process on the amorphous silicon layer includesirradiating the amorphous silicon layer with laser light (e.g., laserlight output from an excimer laser); the amorphous silicon layer absorbslaser light and generates heat, thereby gradually changing from asurface melting state to a completely melting state; during the coolingprocess, the amorphous silicon layer can be transformed into apolysilicon layer. For example, the specific method for performing theannealing process on the amorphous silicon layer can be, for example, anexcimer laser annealing process, and will not be described here again.The crystallization process can also be metal induced crystallization(MIC) process (such as metal lateral induced crystallization (MILC)),solid phase crystallization (SPC) process, sequential lateralcrystallization (SLC) process and other crystallization processes. Forexample, the active layer 116 may be formed by patterning the activethin film layer by forming the active thin film layer. For example, theactive thin film layer may be a planar structure covering the basesubstrate. For example, the active thin film layer may cover at leastthe display region 161 of the array substrate 100.

The active layer 116 of the thin film transistor 112 is made of asemiconductor material. For example, in another example of thisembodiment, the active layer 116 is made of a metal oxide semiconductormaterial including indium gallium zinc oxide (IGZO), zinc oxide, and thelike. After the thin film of the metal oxide semiconductor material isformed, it is annealed to improve the electrical characteristicsthereof.

As described below in connection with FIG. 4D and FIG. 4J, after formingthe active layer 116 of the thin film transistor 112, the lightshielding thin film layer 1130 is patterned to form the lighttransmission holes 114, thereby forming the light shielding layer 113.Because there is no temperature difference caused by the lighttransmission holes 114 of the light-shielding layer in thelight-shielding thin film layer 1130 during the annealing process forthe active layer, there is no need to set a second predetermined pitchPD2 (e.g., 1 micron or 2 microns) corresponding to the annealingtemperature difference between the orthogonal projection of the activelayer 116 of the thin film transistor 112 on the light-shielding layer113 and the light transmission holes 114 of the adjacent light-shieldinglayer. Therefore, the diameter of the light transmission hole 114 of thelight-shielding layer can be correspondingly increased (for example, theradius is increased by 2 microns or 4 microns), thereby improving theintensity of the diffuse reflection light that is from a finger andincident on the imaging device 115 and the signal-to-noise ratio of theimage output by the imaging device 115.

Step S205: a gate insulating thin film layer 1220 of the thin filmtransistor 112 is formed on the active layer 116 (see FIG. 4E).

For example, the gate insulating thin film layer 1220 of the thin filmtransistor 112 may be formed of an inorganic material or an organicmaterial, and the gate insulating thin film layer 1220 may be formed of,for example, organic resin, silicon oxide (SiOx), silicon oxynitride(SiNxOy), or silicon nitride (SiNx), but embodiments of the presentdisclosure are not limited thereto.

Step S206: the first capacitor electrode 141 and the gate electrode 123of the thin film transistor 112 are formed on the gate insulating thinfilm layer 1220 (see FIG. 4F).

For example, the gate electrode 123 and the first capacitor electrode141 of the thin film transistor 112 are both formed of a metal material(e.g., copper, aluminum, or aluminum alloy), but embodiments of thepresent disclosure are not limited thereto. It should be noted thatalthough the gate electrode 123 and the first capacitor electrode 141 ofthe thin film transistor 112 adopt different filling patternsillustrated in FIG. 4F, the gate electrode 123 and the first capacitorelectrode 141 of the thin film transistor 112 can be made of the samematerial to simplify the process and reduce the manufacturing costs. Forexample, as illustrated in FIG. 4F, the thickness of the gate electrode123 and the first capacitor electrode 141 of the thin film transistor112 are different in the direction perpendicular to the array substrate.In another example, the thickness of the gate electrode 123 and thefirst capacitor electrode 141 of the thin film transistor 112 in thedirection perpendicular to the array substrate may also be the same.

Step S207: a passivation thin film layer 1240 of the thin filmtransistor 112 is formed on the gate electrode 123 of the thin filmtransistor 112 (see FIG. 4G).

For example, the passivation film layer 1240 of the thin film transistor112 may be formed of an inorganic material or an organic insulatingmaterial, and the passivation film layer 1240 may be formed of, forexample, organic resin, silicon oxide (SiOx), silicon oxynitride(SiNxOy), or silicon nitride (SiNx), but embodiments of the presentdisclosure are not limited thereto.

Step S208: the first via hole 132 and the third via hole 133 are formedin the passivation thin film layer 1240 of the thin film transistor 112and the gate insulating thin film layer 1220 of the thin film transistor112 (see FIG. 4H).

For example, the first via hole 132 and the third via hole 133 may beformed in the passivation thin film layer 1240 of the thin filmtransistor 112 and the gate insulating thin film layer 1220 of the thinfilm transistor 112 by a patterning process, thereby forming the gateinsulating intermediate layer 1221 and the passivation intermediatelayer 1241. For example, in a case where the array substrate 100 furtherincludes a material of the buffer layer 121, the first via hole 132 andthe third via hole 133 pass through the buffer film layer 1210, therebyforming a buffer interlayer 1211, to expose the light shielding filmlayer 1130.

For example, forming the first via hole 132 and the third via hole 133in the passivation thin film layer 1240 of the thin film transistor 112and the gate insulating thin film layer 1220 of the thin film transistor112 by a patterning process may include the following steps S101- toS103.

Step S101: a layer of photoresist is coated on the passivation filmlayer 1240, and a photoresist pattern is formed after exposure anddevelopment processes.

Step S102: the gate insulating film layer 1220 and the passivation filmlayer 1240 exposed through the photoresist pattern are etched (e.g., dryetching) to form the first via hole 132 and the third via hole 133.

Step S103: the remaining photoresist is removed.

For example, because the first via hole 132 and the third via hole 133can be formed in same one patterning process, there is no need toprovide an additional via hole patterning process for forming the firstvia hole 132 for patterning the light shielding thin film layer 1130,thereby avoiding lowering the manufacturing efficiency of the arraysubstrate 100 and the display device and avoiding increasing themanufacturing costs of the array substrate 100 and the display device.

Step S209: forming a capacitor electrode metal layer 191 on thepassivation intermediate layer 1241 of the thin film transistor 112 (seeFIG. 4I). It should be noted that when forming the capacitor electrodemetal layer 191, the first via hole 132 and the third via hole 133 maybe shielded to prevent the material for forming the capacitor electrodemetal layer 191 from filling the first via hole 132 and the third viahole 133, but embodiments of the present disclosure are not limitedthereto.

Step S210: patterning the capacitor electrode metal layer 191 to formthe second capacitor electrode 142, and in the same process, patterningthe light shielding thin film layer 1130 via the first via hole 132 toform the light transmission hole 114 of the light shielding layer 113(see FIG. 4J).

For example, by patterning the capacitor electrode metal layer 191 andthe light shielding thin film layer 1130 in the same patterning process,it is unnecessary to add an additional patterning process to form thelight transmission hole 114 of the light shielding layer; therefore,under the condition of increasing the diameter of the light transmissionhole 114, the combination of step S210 and step S208 can not onlyeliminate the additional patterning process for forming the first viahole 132 for patterning the light shielding thin film layer 1130, butalso omit the patterning process for the light shielding thin film layer1130 (for forming the light transmission hole 114) in the conventionalmanufacturing method of the array substrate. Thus, in the manufacturingmethod of the array substrate provided by the embodiment of the presentdisclosure, the manufacturing efficiency of the array substrate 100 andthe display device can be further improved (for example, the productioncapacity of the drive backplate or the array substrate can be increasedfrom 24,000 pieces per month to 32,000 pieces per month), and themanufacturing costs of the array substrate 100 and the display devicecan be further reduced.

For example, the capacitor electrode metal layer 191 may be made of thesame material (e.g., molybdenum metal) used to make the light shieldinglayer 113. In this case, even if the capacitor electrode metal layer 191and the light shielding film layer 1130 are patterned in the samepatterning process, because the material properties of the capacitorelectrode metal layer 191 and the light shielding film layer 1130 arethe same, a good etching effect can be obtained.

Step S211: forming an interlayer insulating film layer 1250 on thesecond capacitor electrode 142 (see FIG. 4K).

For example, the interlayer insulating film layer 1250 may be made of atransparent insulating material. For example, the interlayer insulatingfilm layer 1250 may be formed of an inorganic material or an organicmaterial, and the interlayer insulating film layer 1250 may be formedof, for example, an organic resin, silicon oxide (SiOx), siliconoxynitride (SiNxOy), or silicon nitride (SiNx), but embodiments of thepresent disclosure are not limited thereto.

Step S212: forming second via holes 131 in the interlayer insulatingthin film layer 1250, the passivation intermediate layer 1241 of thethin film transistor 112, and the gate insulating intermediate layer1221 of the thin film transistor 112 to expose the source region and thedrain region of the active layer 116, and in the same process, forming asixth via hole 136 and a fourth via hole 134 in the interlayerinsulating thin film layer 1250 to expose the first via hole 132 and thethird via hole 133, respectively (see FIG. 4L), thereby forming thefirst through hole H1, the second through hole H2, and the third throughhole H3.

For example, by a patterning process, forming the second via holes 131in the interlayer insulating thin film layer 1250, the passivationintermediate layer 1241 of the thin film transistor 112, and the gateinsulating intermediate layer 1221, and forming the sixth via hole 136and the fourth via hole 134 in the interlayer insulating thin film layer1250, include the following steps S111- to S113.

Step S111: coating photoresist on the interlayer insulating film layer1250, and forming a photoresist pattern after exposure and developmentprocesses.

Step S112: etching the interlayer insulating thin film layer 1250, thepassivation intermediate layer 1241 and the gate insulating intermediatelayer 1221 of the thin film transistor 112 exposed through thephotoresist pattern (e.g., dry etching) to form the first via hole 132and the third via hole 133.

Step S113: removing the remaining photoresist.

For example, because the second via holes 131, the sixth via hole 136,and the fourth via hole 134 can be formed in the same patterningprocess, there is no need to add an additional patterning process forforming the sixth via hole 136 and the fourth via hole 134 (to exposethe first via hole 132 and the third via hole 133, respectively),thereby improving the manufacturing efficiency of the array substrate100 and the display device, and reducing the manufacturing costs of thearray substrate 100 and the display device.

For example, by forming the first via hole 132 and the sixth via hole136 before and after forming the interlayer insulating layer 125,respectively, the problem that the light shielding layer 113 cannot beexposed through the first via hole 132 due to insufficient etchingdepth, which problem may exist in a single patterning (for example, forforming the first via hole 132 in a patterning process for forming thesecond via holes 131), can be avoided.

For example, in another example, in step S212, when the second via holes131 are formed, the sixth via hole 136 is not formed (i.e., the materialfor forming the interlayer insulating layer 125 filled in the first viahole 132 and the light transmission hole 114 of light-shielding layer instep S211 is not removed), then finally the material of the interlayerinsulating layer 125 fills the first via hole 132 and the lighttransmission hole 114 of the light-shielding layer (see FIG. 5A),whereby interfacial reflection can be reduced, furthermore, theintensity of the diffuse reflection light that is from a finger andincident on the imaging device 115 can be increased, and thesignal-to-noise ratio of the image output by the imaging device 115 canbe increased.

Step S213: forming the source electrode 129 and the drain electrode 126of the thin film transistor 112 to contact the active layer 116 throughthe second via holes 131 in the interlayer insulating layer 125, thepassivation layer 124, and the gate insulating layer 122. Also, in thesame process, the connection electrode 171 is formed to contact thelight shielding layer 113 via the fourth via hole 134 in the interlayerinsulating layer 125 and the third via hole 133 in the passivation layer124, the gate insulating layer 122, and the buffer layer 121 (see FIG.4M).

For example, by forming the connection electrode 171 in the process offorming the source electrode 129 and the drain electrode 126 of the thinfilm transistor 112, not only can parasitic capacitance and warpingeffect of the thin film transistor 112 caused by floating of the lightshielding layer 113 be avoided, but also an additional conductivematerial deposition process and a patterning process need not be added,thus the manufacturing efficiency of the array substrate 100 and thedisplay device can be improved, and the manufacturing costs of the arraysubstrate 100 and the display device can be reduced.

Step S214: forming a planarization layer 127 on the source electrode 129and the drain electrode 126, whereby the sixth via hole 136, the firstvia hole 132, and the light transmission hole 114 of the light-shieldinglayer are filled with the material for forming the planarization layer127 (see FIG. 4N).

For example, the planarization layer 127 may be made of a transparentinsulating material. For example, the planarization layer 127 may beformed of an inorganic material or an organic material, and theplanarization layer 127 may be formed of, for example, an organic resin,silicon oxide (SiOx), silicon oxynitride (SiNxOy), or silicon nitride(SiNx), but embodiments of the present disclosure are not limitedthereto.

For example, by causing the material for forming the planarization layer127 to fill the sixth via hole 136, the first via hole 132, and thelight transmission hole 114 of the light-shielding layer, it is possibleto avoid the decrease in light intensity through the light transmissionhole 114 of the light-shielding layer caused by interfacial reflectionbetween film layers (for example, interfacial reflection includesinterfacial reflection between the buffer layer 121 and the gateinsulating layer 122, interfacial reflection between the passivationlayer 124 and the gate insulating layer 122, interfacial reflectionbetween the interlayer insulating layer 125 and the passivation layer124, and interfacial reflection between the planarization layer 127 andthe interlayer insulating layer 125). Therefore, it is possible tofurther increase the intensity of diffuse reflection light from a fingerincident on the imaging device 115 and improve the signal-to-noise ratioof the image output by the imaging device 115.

Step S215: forming a light emitting element 151 on the side of theplanarization layer 127 away from the base substrate 111. For example,the light emitting element 151 is electrically connected to the sourceelectrode or the drain electrode via the fifth via hole 135 in theplanarization layer 127, whereby the light emitting element 151 can emitlight under the drive of the thin film transistor 112. For example, thelight emitting element 151 may be an organic light emitting diode, butembodiments of the present disclosure are not limited thereto. For thesake of clarity, the manufacturing method of the light emitting element151 will be described later and will not be described in detail here.

Step S216: forming a plurality of spacers 156 at an interval are formedon a side of the light emitting element 151 away from the base substrate111 (on a side surface of the pixel defining layer 155 of the lightemitting element 151 away from the base substrate 111) (see FIG. 4O).

For example, the orthogonal projection of each spacer 156 on the arraysubstrate 100 and the orthogonal projection of the first electrode 152on the array substrate 100 are arranged at an interval, therebypreventing the force applied to the cover plate from being transmittedto the light emitting layer 153, and further ensuring the displayquality of the display panel 10 including the array substrate 100. Forexample, the spacers 156 may be formed before forming the light emittinglayer 153 and the second electrode 154 of the light emitting element151, but embodiments of the present disclosure are not limited thereto;according to actual application requirements, the spacers 156 may alsobe formed after forming the light emitting layer 153 and the secondelectrode 154 of the light emitting element 151.

For example, in other examples, in the case where the array substrate100 does not need to be provided with the connection electrode 171, themanufacturing method of the array substrate does not need to form thethird via hole 133 and the fourth via hole 134 in steps S208 and S212,respectively, and does not need to form the connection electrode 171 instep S213.

For example, in other examples, when the array substrate 100 does notneed to be provided with the first capacitor electrode 141 and thesecond capacitor electrode 142 to form capacitance, the manufacturingmethod of the array substrate does not need to perform steps S209, S210and S211, does not need to form the first capacitor electrode 141 instep S206, and does not need to form the sixth via hole 136 and thefourth via hole 134 in step S212. In this case, the source electrode129, the drain electrode 126 and the connection electrode 171 of thethin film transistor 112 may be disposed on a side surface of thepassivation layer 124 away from the base substrate 111, the sourceelectrode 129 and the drain electrode 126 contacting the active layer116 through the second via holes 131 in the passivation layer 124 andthe gate insulating layer 122, and the connection electrode 171 is incontact with the light shielding layer 113 through the third via hole133 in the passivation layer 124, the gate insulating layer 122, and thebuffer layer 121. In addition, the material of the planarization layer127 fills the first via hole 132 and the light transmission hole 114 ofthe light shielding layer to reduce interfacial reflection and increasethe light intensity incident on the imaging device 515.

For example, the first via hole 132 is not limited to be formed afterforming the passivation layer 124 of the thin film transistor 112 andbefore forming the second capacitor electrode 142 (i.e., before formingthe source electrode 129 and the drain electrode 126). The fabricationsequence of the film layers of the first via hole 132 and the thin filmtransistor 112 can be set according to actual application requirements,and the embodiments of the present disclosure is not specificallylimited to this case.

For example, in other examples, the first via hole 132 may be formed inthe gate insulating layer 122 after forming the gate insulating layer122 and before forming the gate electrode 123, so as to expose the lightshielding layer 113, and the light shielding layer 113 may be patternedthrough the first via hole 132 to form a light transmission hole, forexample, while forming the gate electrode 123. For example, bypatterning the light-shielding layer 113 to form a light transmissionhole after forming the active layer 116 of the thin film transistor 112,the diameter of the light transmission hole 114 of the light-shieldinglayer can be increased, whereby the intensity of the diffuse reflectionlight that is from a finger and incident on the imaging device 115 canbe increased and the signal-to-noise ratio of the image output by theimaging device 115 can be improved. In this case, as illustrated in FIG.5B, the passivation layer 124 may be formed on the gate electrode 123while the first via hole 132 and the light transmission hole 114 of thelight-shielding layer are filled with the material for forming thepassivation layer 124, and then the light transmission hole 114 is notexposed in the process of patterning the interlayer insulating layer 125and the planarization layer 127. Thus, the light transmission hole 114is finally filled with the passivation layer 124 (see FIG. 5B). in theregion corresponding to the light transmission hole 114 of thelight-shielding layer, there is no interface reflection between thebuffer layer 121 and the gate insulating layer 122 and no interfacereflection between the passivation layer 124 and the gate insulatinglayer 122, thereby still increasing the intensity of the diffusereflection light that is from a finger and incident on the imagingdevice 115 to a certain extent and increasing the signal-to-noise ratioof the image output by the imaging device 115.

For example, in other examples, the second via holes 131, the first viahole 132, and the third via hole 133 may also be formed in the gateinsulating layer 122, the passivation layer 124, and the interlayerinsulating layer 125 after the interlayer insulating layer 125 is formedand before the source electrode 129 and the drain electrode 126 areformed. For example, in order to ensure that the etching depth of thefirst via hole 132 and the third via hole 133 are the same and both aregreater than the etching depth of the second via holes 131, a halftonemask etching technique may be used. The specific etching methods can bereferred to the conventional halftone mask etching technique, which willnot be repeated here. For example, by forming the first via hole 132after forming the interlayer insulating layer 125 and before forming thesource electrode 129 and the drain electrode 126, the first via hole 132and the third via hole 133 may be formed only in the patterning processof making the second via holes 131; at this time, not only can thediameter of the light transmission hole 114 of the light-shielding layerbe increased, but also two patterning processes can be reduced;furthermore, the imaging quality can be improved, the manufacturingefficiency of the array substrate 100 and the display device can befurther improved, and the manufacturing costs of the array substrate 100and the display device can be further reduced. In this case, theplanarization layer 127 may be formed on the source electrode 129 andthe drain electrode 126 while filling the first via hole 132 and thelight transmission hole 114 of the light-shielding layer with thematerial for forming the planarization layer 127 (see FIG. 5C), wherebyinterface reflection can be reduced, further the intensity of thediffuse reflection light that is from a finger and incident on theimaging device 115 can be increased, and the signal-to-noise ratio ofthe image output by the imaging device 115 can be increased.

For example, in other examples, after forming the patterned active layer116 as illustrated in FIG. 4D, the buffer layer 121 may be patterned toform a first via hole 132 and a third via hole 133 that expose the lightshielding layer 113, and then the light shielding layer 113 may bepatterned through the first via hole 132 to form the light transmittinghole 114. The first via hole 132 in the buffer layer 121 is then filledby the gate insulating layer 122 (see FIG. 5D), which also causes thelight transmission hole 114 of the light-shielding layer 113 to befilled by the gate insulating layer 122. Thereafter, the lighttransmission hole 114 is not exposed in the process of patterning thepassivation layer 124, the interlayer insulating layer 125 or theplanarization layer 127. Thus, the light transmission hole 114 isfinally filled by the gate insulating layer 122 (see FIG. 5D). In theregion corresponding to the light transmission hole 114 of thelight-shielding layer, there is no interfacial reflection between thebuffer layer 121 and the gate insulating layer 122, thus the intensityof the diffuse reflection light that is from a finger and incident onthe imaging device 115 can still be increased to a certain extent, andthe signal-to-noise ratio of the image output by the imaging device 115can be increased. For example, while the light-shielding layer 113 ispatterned through the first via hole 132 to form the light transmissionhole 114, another hole may be formed by patterning the light-shieldinglayer 113 through the third via hole 133. In this case, the connectionelectrode 171 in FIG. 5D will be filled into the additional hole so asto be electrically connected with the light shielding layer 1130.

For example, the manufacturing method of the light emitting element 151provided in an embodiment of the present disclosure will be exemplarilydescribed below with reference to FIG. 4O. For example, as illustratedin FIG. 4O, forming the light emitting element 151 on the side of theplanarization layer 127 away from the base substrate 111 includes thefollowing steps S121- to S126.

Step S121: forming a fifth via hole 135 in the planarization layer 127(see FIG. 4O).

For example, the specific method of forming the fifth via hole 135 inthe planarization layer 127 may refer to steps S101- to S103, and willnot be described here.

Step S122: forming a first electrode 152 of the light emitting element151, whereby the first electrode 152 is in contact with the sourceelectrode or the drain electrode 126 of the thin film transistor 112 viathe fifth via hole 135 (see FIG. 4O).

For example, the first electrode 152 may be an anode, but embodiments ofthe present disclosure are not limited thereto. For example, the firstelectrode 152 may include a reflective electrode, whereby light emittedfrom the light emitting element 151 can be reflected to the displayside, thereby improving the light emitting efficiency of the lightemitting element 151 and reducing the influence on the imaging device115. For example, the first electrode 152 may be made of a stack ofindium tin oxide (ITO) and a metal layer, but embodiments of the presentdisclosure are not limited thereto.

Step S123: forming a pixel defining layer 155 on the first electrode 152(see FIG. 4O).

For example, the pixel defining layer 155 may be made of a transparentinsulating material, but embodiments of the present disclosure are notlimited thereto.

Step S124: patterning the pixel defining layer 155 and forming anopening in the pixel defining layer 155 to expose the first electrode152 (see FIG. 4O).

For example, the pixel defining layer 155 may be patterned by apatterning process to form an opening in the pixel defining layer 155,but embodiments of the present disclosure are not limited thereto.

Step S125: forming a light emitting layer 153 of the light emittingelement 151 on the first electrode 152.

For example, the light emitting layer 153 may emit light, and thewavelength of the emitted light depends on the material from which thelight emitting layer 153 is made. The light emitting layer 153 may emitred light, green light or blue light, for example, whereby in the casewhere the light emitting layer 153 includes a plurality of lightemitting units, the display panel can display a color image.

For example, the manufacturing material of the light emitting layer 153can be selected according to actual application requirements, and theembodiments of the present disclosure are not specifically limited tothis. For example, the material for making the light emitting layer 153includes an organic fluorescent light emitting material or an organicphosphorus light emitting material. For example, for organic fluorescentluminescent materials, a luminescent material containing at least one ofDCM, DCJT, DCJ, DCJT, etc. can emit red light; a luminescent materialcontaining at least one of C-545T (coumarin), C-545MT, quinacridone(QA), polyaromatic hydrocarbon (PAH) and the like can emit green light;a luminescent material containing at least one of TBP, DSA-Ph, BD1, BD2and the like can emit blue light; for organic fluorescent luminescentmaterials containing both DCJTB and TBP, white light can be emitted. Fororganophosphorus luminescent materials, a luminescent materialcontaining at least one of PtOEP, Btp₂Ir(acac), Ir(piq)₂(acac) and thelike can emit red light; a luminescent material containing at least oneof Ir(ppy)₃, Ir(mppy)₃, (ppy)₂ Ir(acac) and the like can emit greenlight; a luminescent material containing at least one of FIrpic, FIrtaz,FIrN4 and other materials can emit blue light.

Step S126: forming a second electrode 154 on the light emitting layer153 (see FIG. 4O). For example, when the first electrode 152 and thesecond electrode 154 are respectively applied with voltages, the lightemitting layer 153 may emit light.

For example, in a case where the first electrode 152 may be an anode,the second electrode 154 may be a cathode, but embodiments of thepresent disclosure are not limited thereto. For example, the secondelectrode 154 may be made of a transparent conductive material or ametal with a relatively thin thickness so that the second electrode 154has a transparent or translucent property (for example, the secondelectrode 154 may be made of a transparent conductive oxide material anda transparent alloy material, respectively), but embodiments of thepresent disclosure are not limited thereto.

The embodiments of the disclosure provide an array substrate, amanufacturing method thereof, a display panel and a display device. Thearray substrate, the manufacturing method thereof, the display panel andthe display device can improve the imaging quality.

As illustrated in FIG. 4O and FIG. 5C, the insulating layer ISL is abuffer layer 121, a passivation layer 124, a gate insulating layer 122,and an interlayer insulating layer 125, and the planarization layer 127is a filling layer FL. The first through hole H1 penetrates through thebuffer layer 121, the passivation layer 124, the gate insulating layer122, and the interlayer insulating layer 125.

As illustrated in FIG. 5A, the insulating layer ISL is a buffer layer121, a passivation layer 124, and a gate insulating layer 122, and theinterlayer insulating layer 125 is a filling layer FL. The first throughhole H1 penetrates through the buffer layer 121, the passivation layer124, and the gate insulating layer 122.

As illustrated in FIG. 5B, the insulating layer ISL is a buffer layer121 and a gate insulating layer 122, and the filling layer FL is apassivation layer 124. The first through hole H1 penetrates through thebuffer layer 121 and the gate insulating layer 122.

As illustrated in FIG. 5D, the insulating layer ISL is a buffer layer121, and the filling layer FL is a gate insulating layer 122. The firstthrough hole H1 penetrates the buffer layer 121.

In FIG. 4O and FIG. 5A to FIG. 5D, the second through hole H1 penetratesthrough the passivation layer 124, the gate insulating layer 122, andthe interlayer insulating layer 125. The third through hole H3penetrates the buffer layer 121, the passivation layer 124, the gateinsulating layer 122, and the interlayer insulating layer 125.

The following points need to be explained:

(1) In the drawings of the embodiments of the present invention, onlythe structures related to the embodiments of the present invention areinvolved, and other structures may refer to common designs.

(2) For the sake of clarity, in the drawings used to describeembodiments of the present invention, the thickness and dimensions ofthe layers or structures are exaggerated. It will be understood thatwhen an element such as a layer, film, region or substrate is referredto as being “on” or “under” another element, the element may be“directly” on “or” under “the other element, or intervening elements maybe present.

(3) Without conflict, the features in the same embodiment and differentembodiments of the present invention can be combined with each other.

Although the present disclosure has been described in detail withgeneral descriptions and specific embodiments above, it will be obviousto those skilled in the art that some modifications or improvements canbe made based on the embodiments of the present disclosure. Therefore,all such modifications or improvements made without departing from thespirit of this disclosure are within the scope of protection claimed inthis disclosure.

The above description is merely an exemplary embodiment of the presentdisclosure and is not intended to limit the scope of protection of thepresent disclosure, which is determined by the appended claims.

1. An array substrate comprising: a base substrate; a light shieldinglayer, which is on the base substrate and comprises a light transmissionhole; an active layer of a thin film transistor, at one side of thelight shielding layer away from the base substrate; and an insulatinglayer on the base substrate, the insulating layer including a firstthrough hole, the first through hole being in communication with thelight transmission hole.
 2. The array substrate according to claim 1,wherein an orthogonal projection of the first through hole on the basesubstrate and an orthogonal projection of the active layer on the basesubstrate do not overlap.
 3. The array substrate according to claim 1,wherein the orthogonal projection of the light transmission hole on thebase substrate is completely within an orthogonal projection of thefirst through hole on the base substrate.
 4. The array substrateaccording to claim 1, further comprising a filling structure, whereinthe filling structure is filled in the first through hole and the lighttransmission hole.
 5. The array substrate according to claim 4, whereinthe first through hole and the light transmission hole are completelyfilled by the filling structure.
 6. The array substrate according toclaim 4, further comprising a filling layer, wherein the filling layeris located on a side of the insulating layer away from the basesubstrate, and the filling structure is integrally formed with thefilling layer.
 7. The array substrate according to claim 6, wherein thefilling layer comprises any one of a group consisting of a passivationlayer, a gate insulating layer, an interlayer insulating layer, and aplanarization layer.
 8. The array substrate according to claim 1,wherein the insulating layer comprises at least one of a groupconsisting of a buffer layer, a passivation layer, a gate insulatinglayer, and an interlayer insulating layer.
 9. The array substrateaccording to claim 8, further comprising a source electrode and a drainelectrode, wherein the source electrode and the drain electrode arerespectively connected to the active layer through second through holespenetrating at least one of the passivation layer, the gate insulatinglayer and the interlayer insulating layer.
 10. The array substrateaccording to claim 8, further comprising a connection electrode, whereinthe connection electrode is connected to the light shielding layerthrough a third through hole penetrating at least one of the bufferlayer, the passivation layer, the gate insulating layer, and theinterlayer insulating layer.
 11. (canceled)
 12. The array substrateaccording to claim 1, further comprising an imaging device on a side ofthe base substrate away from the light shielding layer, wherein theimaging device at least partially overlaps the light transmission holein a direction perpendicular to the base substrate.
 13. A display panelcomprising the array substrate according to claim
 1. 14. A displaydevice comprising the display panel according to claim
 13. 15. Amanufacturing method of an array substrate, comprising: providing a basesubstrate; forming a light shielding film layer on the base substrate;forming an active layer of a thin film transistor on the light shieldingthin film layer; and after the active layer is formed, patterning thelight shielding film layer to form a light shielding layer, wherein thelight shielding layer comprises a light transmission hole.
 16. Themanufacturing method of the array substrate according to claim 15,further comprising: forming an insulating layer, patterning theinsulating layer to form a first through hole therein, patterning thelight shielding thin film layer through the first through hole to formthe light transmission hole, wherein an orthogonal projection of thefirst through hole on the base substrate and an orthogonal projection ofthe active layer on the base substrate do not overlap.
 17. Themanufacturing method of the array substrate according to claim 16,further comprising: forming a filling structure, wherein the fillingstructure is filled in the first through hole and the light transmissionhole.
 18. (canceled)
 19. The manufacturing method of the array substrateaccording to claim 17, further comprising forming a filling layer on theinsulating layer, wherein the filling structure is part of the fillinglayer.
 20. The manufacturing method of the array substrate according toclaim 19, wherein the filling layer comprises any one of a groupconsisting of a passivation layer, a gate insulating layer, aninterlayer insulating layer, and a planarization layer.
 21. Themanufacturing method of the array substrate according to claim 16,wherein forming the insulating layer comprises forming at least one of agroup consisting of a buffer film layer, a passivation film layer, agate insulating film layer, and an interlayer insulating film layer. 22.The manufacturing method of the array substrate according to claim 21,further comprising: forming a connection electrode and forming a thirdthrough hole penetrating at least one of the buffer film layer, thepassivation film layer, the gate insulating film layer, and theinterlayer insulating film layer, wherein the connection electrode isconnected to the light shielding layer through the third through hole.23. (canceled)